About the role
L3Harris is dedicated to recruiting and developing high-performing talent who are passionate about what they do. Our employees are unified in a shared dedication to our customers’ mission and quest for professional growth. L3Harris provides an inclusive, engaging environment designed to empower employees and promote work-life success. Fundamental to our culture is an unwavering focus on values, dedication to our communities, and commitment to excellence in everything we do.
L3Harris is the Trusted Disruptor in defense tech. With customers’ mission-critical needs always in mind, our employees deliver end-to-end technology solutions connecting the space, air, land, sea and cyber domains in the interest of national security.
Job Location: Clifton, NJ
Job Schedule: 9/80: Employee works 9 out of every 14 days – totaling 80 hours worked – and have every other Friday off
Job Description
L3Harris EW in Clifton, NJ has an immediate need for highly motivated FPGA design engineer. In this role you will develop, simulate, and integrate in lab highly specialized firmware designs targeting electronic warfare systems. Responsibilities include generation of firmware derived requirements, architecture of digital solutions to meet said requirements and formal test / lab verification of the functional system. The qualified candidate is able to work semi-autonomously as a lead designer, potentially driving a small team of firmware engineers through coding, simulation, code analysis, and circuit card design support.
Essential Functions
Provide leadership and Subject Matter Expertise for the development of high reuse and easily extensible EW technology.
Develop Signal Processing Architectures targeting single chip and distributed chip low latency signal classification and countermeasures.
Work cross-functionally to adopt an efficient, common, mission specific, best practices derived, development process.
Work with a variety of firmware, software, and systems development teams, assuring requirements are verified in a consistent fashion prior to firmware delivery to Integration.
Decompose and allocate system and box-level requirements to FPGA specifications.
Architect High Com…
